Chemical mechanical planarization (“CMP”) is widely used in the microelectronics industry. A typical CMP process involves polishing back built up insulating layers of insulators or conductors on integrated circuit chips during manufacture.
More particularly, a resinous polishing pad having a cellular structure is employed in conjunction with a slurry, for example a water-based slurry comprising colloidal silica particles. When pressure is applied between the polishing pad in the workpiece (e.g., silicon wafer) being polished, mechanical stresses are concentrated on the exposed edges of the adjoining cells in the cellular pad. Abrasive particles within the slurry concentrated on these edges tend to create zones of localized high stress at the workpiece in the vicinity of the exposed edges of the polishing pad. This localized pressure creates mechanical strain on the chemical bonds comprising the surface being polished, rendering the chemical bonds more susceptible to chemical attack or corrosion (e.g., stress corrosion). Consequently, microscopic regions are removed from the surface being polished, enhancing planarity of the polished surface. See, for example, Arail et al., U.S. Pat. No. 5,099,614, issued March, 1992; Karlsrud, U.S. Pat. No. 5,498,196, issued March, 1996; Arai, et al., U.S. Pat. No. 4,805,348, issued February, 1989; Karlsrud et al., U.S. Pat. No. 5,329,732, issued July, 1994; and Karlsrud et al, U.S. Pat. No. 5,498,199, issued March, 1996. For a further discussion of presently known lapping and planarization techniques. By this reference, the entire disclosures of the foregoing patents are hereby incorporated herein.
Presently known polishing techniques are unsatisfactory in several regards. For example, as the size of microelectronic structures used in integrated circuits decreases, and further as the number of microelectronic structures on current and future generation integrated circuits increases, the degree of planarity required increases dramatically. For example, the high degree of accuracy of current lithographic techniques or smaller devices requires increasingly flatter surfaces. Presently known polishing techniques are believed to be inadequate to produce the degree of planarity and uniformity across the relatively large surfaces of silicon wafers used in integrated circuits, particularly for future generations.
Presently known polishing techniques are also unsatisfactory in that the cellular structure of the polishing pad tends to generate heat at the interface between the pad and the workpiece. The presence of heat is problematic in that it tends to dry the slurry in the vicinity of large workpiece centers. As a polishing pad moves radially inward across the surface of a circular wafer, it has been observed that the slurry can dehydrate unevenly across the surface of the workpiece. Consequently, the polishing effect of the pad can be non-uniform across the surface of the workpiece, resulting in non-uniform planarization effects.
Chemical mechanical planarization techniques and materials are thus needed which will permit a higher degree of planarization and uniformity of that planarization over the entire surface of integrated circuit structures.